DESIGN A HIGH-PRECISION VLSI ARCHITECTURE OF RECONFIGURABLE FFT PROCESSOR

Abstract

This article details the configuration of a reconfigurable fast-forward processor based on a very large-scale
integrated (VLSI) architecture. Typically used in systems that involve long-term evolution, FFT essentially
supports the bit size that is suited to the system. The size of the fault-free FFT processor may be customised
using transport-triggered architecture. In this case, we use the gold standard of cell technology to assess both
performance and energy efficiency. In order to access main memory, the computing address unit creates the
address. To move bits around, a barrel shifter is used. The bits will be merged extremely well by the data merging
block. The data memory blocks store all the combined and shifter data. When accessing the reconfigurable unit,
data will be controlled by the memory access controller. The twiddle factor is a tool for making systems run
faster. The simulation results show that the reconfigurable FFT processor does, in fact, provide useful results.