Design and Analysis of Multi-Protocol Conversion Unit for SPI, I2C and UART

Abstract

The rapid proliferation of heterogeneous embedded systems has created an acute demand for intelligent
hardware that can seamlessly bridge fundamentally different serial communication protocols. Modern Internet of
Things (IoT) nodes, industrial automation platforms, automotive electronics, and medical instrumentation routinely
require simultaneous interfacing with sensors, actuators, and processing elements that each expose a different
communication standard. The absence of a unified, hardware-level protocol conversion fabric forces system
designers to resort to inefficient software-driven translation layers that introduce latency, consume excessive
processing bandwidth, and fail to scale with increasing data throughput requirements.
This thesis presents the complete design, implementation, and analysis of a Multi-Protocol Conversion Unit
(MPCU) capable of performing bidirectional, low-latency conversion between three of the most widely deployed
synchronous and asynchronous serial communication protocols: Serial Peripheral Interface (SPI), Inter-Integrated
Circuit (I2C), and Universal Asynchronous Receiver-Transmitter (UART). The proposed architecture is described
entirely in synthesizable Register-Transfer Level (RTL) Verilog, enabling direct implementation on commercially
available Field-Programmable Gate Arrays (FPGAs) or integration into custom Application-Specific Integrated
Circuit (ASIC) flows
The MPCU comprises five primary functional blocks: a configurable SPI master controller supporting all
four SPI modes (CPOL/CPHA combinations), a standard- and fast-mode I2C master controller with 7-bit addressing
and ACK/NACK detection, a UART transceiver with 16x oversampling, selectable baud rates up to 115,200 bps, and
configurable parity, an eight-entry per-channel FIFO buffering mechanism, and a centralized protocol bridge
arbitration and conversion state machine. The entire design is parameterized for flexibility and governed by a
lightweight memory-mapped configuration register interface.