FRONT DESIGN AND IMPLEMENTATION OF HIGH SPEED HYBRID DUAL D-FIFO-FF (FLIP-FLOP) SYNCHRONIZER USING VERILOG

Abstract

It is necessary to measure distinct phases for the intended application when the signal and its associated 
data must be maintained simultaneously. Traditional methods would use a mixed-signal technique that 
focusses on time and phase measurements. This introduces ambiguity into the various stages with 
respect to the signals that have been retrieved. We implement the unique design logic core, including 
a synchroniser and a digital phase detector module, for a phase measurement system that offers greater 
resolution and better accuracy within a certain range of several Pico seconds. This allows us to begin 
such complexities, which are directly connected to phase shift changes in FPGA. Systematic sampling 
over the phase detected signal would result from module level adjustments, as we estimate their design 
utilising Dual D-flip flops in this design scenario for the synchroniser and phase detector. We 
compared our design to the current system synchroniser and found that our Dual D-FF architecture 
adequately estimated the model's power consumption and area requirements for each test benchmark. 
In order to highlight the most likely outcome for the observed synchronised values and their phase 
detection via the use of a Dual D flip-flop, the design is assessed using mathematical modelling. The 
Verilog HDL language and the HDL designer series are used to execute our design process. The Xilinx 
Spartan 3 XCS 200TQ-144 is used for modelling the netlist analysis