DESIGN AND IMPLEMENTATION OF AREA EFFICIENT LATTICE BASED CRYPTOGRAPHY

Abstract

The foundations of computer security are being progressively eroded as a result of the current
upsurge in technological improvement, which exposes computer systems and sensitive data to unauthorised users.
Indeed, this necessitated ground-breaking developments necessitating many cryptographic paradigms and
security protocols. Because of its proven security under certain worst-case hardness assumptions and its resilience
to quantum attacks, lattice-based encryption is gaining popularity. Due to the novelty of the subject, researchers
are actively seeking for more effective hardware designs for lattice-based cryptographic building blocks. As a
result, this research suggests implementing hardware efficient lattice based encryption. To optimise the area for
the most crucial and insensitive operating applications, this lattice-based cryptography architecture is built
utilising the Number Transform Theory (NTT). The suggested hardware designs may lessen the amount of
memory accessed, the number of used memory blocks, and slice utilisation via the use of enhanced memory
organisation and simpler address creation. The suggested hardware designs are smaller, require fewer memory
blocks, and have comparable performance to previous work—all while fitting inside the smallest Xilinx Spartan6 FPGA.