Low Power Crypto-chip Design for IoT Applications

Abstract

Cryptography is fundamental to ensuring data security and integrity in modern digital
communications. While numerous algorithms have been developed for data encoding and
decoding, the Advanced Encryption Standard (AES) emerged as a robust solution for securing
large and confidential datasets where existing algorithms proved inadequate. Initially designed to
protect highly sensitive information, AES has become widely adopted in networking applications
as the standard for data protection. This paper presents a low-power crypto-chip design for IoT
applications implementing the AES algorithm using Verilog HDL. AES operates on 16-byte
blocks with variable key sizes ranging from 128 to 256 bits. The implementation leverages
Verilog's advantages over standard VHDL, offering significantly reduced operation time and
propagation delay for encoding and decoding operations. Unlike its predecessor DES (Data
Encryption Standard), which suffered from a fixed 56-bit key size limitation, AES provides
flexibility through variable key sizes, enhancing security while maintaining computational
efficiency. The proposed design achieves 4635 LUTs with a delay of 6.548 ns, demonstrating the
feasibility of hardware-accelerated cryptographic operations for resource-constrained IoT devices.