Design of an Energy-Efficient Reverse Carry Propagate Approximate Adder for Low-Power DSP Architectures

Abstract

Digital Signal Processing (DSP) architectures demand high-speed arithmetic units with low power consumption. Adders are fundamental components in DSP systems and significantly influence overall energy efficiency. Conventional accurate adders consume substantial power due to long carry propagation paths. Approximate computing has emerged as an effective technique for reducing power and delay by relaxing accuracy requirements. This work presents the design of an energy-efficient reverse carry propagate approximate adder (RCPAA) for low-power DSP applications. The proposed adder reverses the direction of carry propagation to reduce critical path delay. Approximation is introduced in the least significant bits to minimize power consumption. The design achieves a balance between accuracy and energy efficiency. Reduced switching activity leads to lower dynamic power. The adder is suitable for error-tolerant DSP applications. Performance is evaluated in terms of power, delay, and area. Simulation results demonstrate significant energy savings. The proposed architecture outperforms conventional adders. It is compatible with modern VLSI design flows.