1.
FRONT DESIGN AND IMPLEMENTATION OF HIGH SPEED HYBRID DUAL D-FIFO-FF (FLIP-FLOP) SYNCHRONIZER USING VERILOG. IJARR [Internet]. 2020 Sep. 20 [cited 2026 Jul. 16];5(9):93-108. Available from: https://www.ijarr.org/index.php/ijarr/article/view/760